1. Field of the Invention
The present invention relates to computing systems, and more particularly, to processing frames at high speeds.
2. Background of the Invention
Computing systems typically include several functional components. These components may include a central processing unit (CPU), main memory, input/output (“I/O”) devices, and streaming storage devices (for example, tape drives). In conventional systems, the main memory is coupled to the CPU via a system bus or a local memory bus. The main memory is used to provide the CPU access to data and/or program information that is stored in main memory at execution time. Typically, the main memory is composed of random access memory (RAM) circuits. A computer system with the CPU and main memory is often referred to as a host system.
Host systems often communicate with peripheral devices via an interface such as the Peripheral Component Interconnect (“PCI”) interface, a local bus standard using parallel data transfer that was developed by Intel Corporation®, or the extension of PCI known as PCI-X. More recently, PCI Express, a standard interface incorporating PCI transaction protocols at the logical level, but using serial data transfer at the physical level has been developed to offer better performance than PCI or PCI-X.
Host systems are used in various network applications, including TCP/IP networks, storage area networks (“SANs”), and various types of external device attachment. In SANs, plural storage devices are made available to various host computing systems. Data is typically moved between plural host systems and storage systems (or storage devices, used interchangeably throughout this specification). The connectivity between a host system and networks or external devices is provided by host bus adapters (“HBAs”), which plug into the host system. HBAs may attach to the host system via a standard interface such as PCI/PCI-X or PCI Express.
HBAs receive serial data streams (bit streams), align the serial data and then convert it into parallel data for processing, as described above. HBAs operate as transmitting devices as well as receiving devices.
PCI Express is an Input/Output (“I/O”) bus standard (incorporated herein by reference in its entirety) that is compatible with existing PCI cards using the PCI Express bus. PCI Express uses discrete logical layers to process inbound and outbound information.
Various other standard interfaces are also used to move data between host systems and peripheral devices. Fibre Channel is one such standard. Fibre Channel (incorporated herein by reference in its entirety) is an American National Standard Institute (ANSI) set of standards, which provides a serial transmission protocol for storage and network protocols.
Networks in general and SANs in particular are now expected to operate at high speeds, for example, at a rate greater than 4 Gigabits per second (“GB”) (for example, 10 GB). HBAs often use an elasticity receive first in first out (“FIFO”) buffer memory to stage incoming frames from the Fibre Channel network. When frames enter an HBA at high speeds, it is difficult to insert or delete fill words to avoid overflow or underflow conditions. Fill words are standard characters (for example, “IDLE”) that are included in a data stream.
If the rate at which frames enter the FIFO is higher than the rate at which the FIFO is read, then the FIFO can over flow (or overrun). If the rate at which the FIFO is filled is lower than the rate at which the FIFO is being read, then the FIFO can be under run (or under flow).
HBAs operating at high speeds may have to widen the local bus, for example, for a HBA supporting a 10 GB link may have to use a 64-bit bus. A serial/de-serializer (“SERDES”) is used to extract a receive clock (Rx_Clk) from incoming frames (i.e. frames that enter the HBA). Data is read from the FIFO at a different clock (may be called a system clock and is also referred to as FPM Clock) than the Rx_CLK. Although a 64-bit data stream enters the HBA, 32-bit patterns are processed by most HBA components. The clock difference coupled with the difference between the 64-bit and 32-bit pattern, makes it difficult to insert/delete fill words to avoid overflow and under flow conditions in high data throughput environments (for example, a network using a 10 GB link).
Conventional FIFO schemes fail to solve the over flow/under flow conditions and hence fail to meet the demands imposed by high operational speeds (for example, a speed of 10 GB).
Therefore, there is a need for a method and system in a HBA that can operate with frequency mismatch conditions of a wider bus and also operate efficiently so that it does not over flow/under flow.